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Reconfigurable Computing

Mikhail Asiatici and Paolo Ienne. Stop crying over your cache miss rate: Handling efficiently thousands of outstanding misses in FPGAs. In Proceedings of the 27th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2019. To appear.

Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Speculative dataflow circuits. In Proceedings of the 27th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2019. To appear.

Stefan Nikolić, Anastasiia Kucherenko, and Paolo Ienne. On feasibility of FPGAs without dedicated programmable interconnect structure. In Proceedings of the 27th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2019. Abstract only; to appear.

Andrea Guerrieri, Sahand Kashani-Akhavan, Pasquale Lombardi, Bilel Belhadj, and Paolo Ienne. A dynamically reconfigurable platform for high-performance and low-power on-board processing. In Proceedings of the 12th NASA/ESA Conference on Adaptive Hardware and Systems, pages 74-81, Edinburgh, August 2018.

Lana Josipović, Radhika Ghosal, and Paolo Ienne. Dynamically scheduled high-level synthesis. In Proceedings of the 26th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 127-36, Monterey, Calif., February 2018. Best Paper Award Nominee.

Mikhail Asiatici, Damian Maiorano, and Paolo Ienne. FPGAs in the datacenters: the case of parallel hybrid super scalar string sample sort (pHS5). In Proceedings of the 26th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, page 294, Monterey, Calif., February 2018. Abstract only.

Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, and Paolo Ienne. LEOSoC: An open-source cross-platform embedded Linux library for managing hardware accelerators in heterogeneous systems-on-chip. In Proceedings of the 26th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, page 295, Monterey, Calif., February 2018. Abstract only.

Lana Josipović, Philip Brisk, and Paolo Ienne. From C to elastic circuits. In Proceedings of the 51st Annual Asilomar Conference on Signals, Systems, and Computers, pages 121-25, Pacific Grove, Calif., October 2017.

Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Seoul, Korea, October 2017. See ACM TECS paper below. Best Paper Award Nominee.

Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. ACM Transactions on Embedded Computing Systems (TECS), 16(5s):125:1–125:19, September 2017.

Nadeen Yassir Gebara, Paolo Ienne, and Kermin Fleming. Spatial memory trace prediction. In Proceedings of the Fourth International Workshop on FPGAs for Software Programmers, pages 48–57, Ghent, Belgium, September 2017. VDE.

Grace Zgheib and Paolo Ienne. Evaluating FPGA clusters under wide ranges of design parameters. In Proceedings of the 27th International Conference on Field-Programmable Logic and Applications, Ghent, Belgium, September 2017. Best Paper Award Nominee.

Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, and Pierre-Emmanuel Gaillardon. Improving circuit mapping performance through MIG-based synthesis for carry chains. In Proceedings of the 27th ACM Great Lakes Symposium on VLSI, pages 131–36, Banff, Canada, May 2017.

Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. In Proceedings of the 25th IEEE Symposium on Field-Programmable Custom Computing Machines, pages 17–20, Napa, Calif., April 2017.

Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, and Haigang Yang. NAND-NOR: A compact, fast, and delay balanced FPGA logic element. In Proceedings of the 25th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 135–40, Monterey, Calif., February 2017.

Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, and Paolo Ienne. Virtualized execution runtime for FPGA accelerators in the cloud. IEEE Access, 5:1900–10, February 2017.

Grace Zgheib and Paolo Ienne. Automatic wire modeling to explore novel FPGA architectures. In Proceedings of the IEEE International Conference on Field Programmable Technology, pages 181–84, Xi’an, China, December 2016.

Lana Josipović, Nithin George, and Paolo Ienne. Enriching C-based high-level synthesis with parallel pattern templates. In Proceedings of the IEEE International Conference on Field Programmable Technology, pages 177–80, Xi’an, China, December 2016.

Paolo Ienne, Walid A. Najjar, Jason Anderson, Philip Brisk, and Walter Stechele. Preface. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications, page 1, Lausanne, Switzerland, August 2016.

Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, and Paolo Ienne. Designing a virtual runtime for FPGA accelerators in the cloud. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications, pages 1–2, Lausanne, Switzerland, August 2016.

Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, and Paolo Ienne. FPRESSO: Enabling express transistor-level exploration of FPGA architectures. In Proceedings of the 24th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 80-89, Monterey, Calif., February 2016. Best Paper Award.

Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, and Paolo Ienne. Improved carry-chain mapping for the VTR flow. In Proceedings of the 2015 International Conference on Field Programmable Technology, pages 80-87, Queenstown, New Zealand, December 2015.

Grace Zgheib, Hadi Parandeh-Afshar, David Novo, and Paolo Ienne. And-inverter cones. In Pierre-Emmanuel Gaillardon, editor, Reconfigurable Logic: Architecture, Tools, and Applications, chapter 5, pages 127-48. CRC, 2015.

Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Liqun Yang, Zhihong Huang, Haigang Yang, and Paolo Ienne. A technology mapper for depth-constrained FPGA logic cells. In Proceedings of the 25th International Conference on Field-Programmable Logic and Applications, pages 1-8, London, September 2015.

Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, and Paolo Ienne. Automatic support for multi-module parallelism from computational patterns. In Proceedings of the 25th International Conference on Field-Programmable Logic and Applications, pages 1-8, London, September 2015.

João Andrade, Nithin George, Kimon Karras, David Novo, Vitor Silva, Paolo Ienne, and Gabriel Falcao. From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. In Proceedings of the 25th International Conference on Field-Programmable Logic and Applications, pages 1-8, London, September 2015.

Muhsen Owaida, Gabriel Falcao, Joao Andrade, Christos Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, and Paolo Ienne. Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs. ACM Transactions on Embedded Computing Systems (TECS), 14(2):33:1-33:23, March 2015.

Jing Huang, Yuanjie Huang, Yunji Chen, Paolo Ienne, Olivier Temam, and Chengyong Wu. A low-cost memory interface for high-throughput accelerators. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, New Delhi, October 2014.

Nithin George, Hyoukjoong Lee, David Novo, Tiark Rompf, Kevin Brown, Arvind Sujeeth, Martin Odersky, Kunle Olukotun, and Paolo Ienne. Hardware system synthesis from domain-specific languages. In Proceedings of the 23rd International Conference on Field-Programmable Logic and Applications, Munich, September 2014.

Walid A. Najjar and Paolo Ienne. Guest Editor’s Introduction: Reconfigurable computing. IEEE Micro, 34(1):4-6, January–February 2014.

Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo Bruna, Hadi Parandeh-Afshar, Haigang Yang, and Paolo Ienne. Revisiting And-Inverter Cones. In Proceedings of the 22nd ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, pages 45-54, Calif., February 2014.

Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, and Paolo Ienne. Shadow And-Inverter cones. In Proceedings of the 23rd International Conference on Field-Programmable Logic and Applications, pages 1-4, Porto, Portugal, September 2013.

Mirjana Stojilović, David Novo Bruna, Lazar Saranovac, Philip Brisk, and Paolo Ienne. Selective flexibility: Creating domain-specific reconfigurable arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-32(5):681-94, May 2013.

Madhura Purnaprajna and Paolo Ienne. A case for heterogeneous technology mapping: Soft versus hard multiplexers. In Proceedings of the 21st IEEE Symposium on Field-Programmable Custom Computing Machines, Seattle, Wash., April 2013.

Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, and Chengyong Wu. Elastic CGRAs. In Proceedings of the 21st ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 171-80, Monterey, Calif., February 2013.

Hadi Parandeh-Afshar, Grace Zgheib, David Novo Bruna, Madhura Purnaprajna, and Paolo Ienne. Shadow AICs: Reaping the benefits of And-Inverter Cones with minimal architectural impact. In Proceedings of the 21st ACM/SIGDA International Symposium on Field Programmable Gate Arrays, page 279, Monterey, Calif., February 2013.

Mirjana Stojilović, David Novo Bruna, Lazar Saranovac, Philip Brisk, and Paolo Ienne. Selective flexibility: Breaking the rigidity of datapath merging. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Dresden, pages 1543-48, March 2012.

Hadi Parandeh-Afshar, Hind Benbihi, David Novo Bruna, and Paolo Ienne. Rethinking FPGAs: Elude the flexibility excess of LUTs with And-Inverter Cones. In Proceedings of the 20th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2012. Best Paper Award.

Yehdhih Ould Mohammad Moctor, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy Lemieux, and Philip Brisk. Reducing the cost of floating-point mantissa alignment and normalization in FPGAs.  In Proceedings of the 20th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2012.

Madhura Purnaprajna and Paolo Ienne. Modifying the FPGA fabric to suit systems with soft VLIW processors. ACM Transactions on Architecture and Code Optimization (TACO), 8(4):33:1-33:16, January 2012.

Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, and Paolo Ienne. Compressor tree synthesis on commercial high-performance FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 4(4):39:1-39:19, December 2011.

Hadi Parandeh-Afshar and Paolo Ienne. Measuring and reducing the performance gap between embedded and soft multipliers on FPGAs. In Proceedings of the 21st International Conference on Field-Programmable Logic and Applications, Chania, Greece, September 2011.

Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, and Paolo Ienne. Routing wire optimization through generic synthesis on FPGA carry chains. In Proceedings of the 20th International Workshop on Logic and Synthesis, San Diego, Calif., June 2011.

Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, and Paolo Ienne. Reducing the pressure on routing resources of FPGAs with generic logic chains. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 237-46, Monterey, Calif., February 2011.

Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne. Synthesis of floating-point addition clusters on FPGAs using carry-save arithmetic. In Proceedings of the 20th International Conference on Field-Programmable Logic and Applications, pages 19-24, Milano, August 2010.

Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, and Paolo Ienne. Improved synthesis of compressor trees on FPGAs by a hybrid and systematic design approach. In Proceedings of the 19th International Workshop on Logic and Synthesis, pages 193-200, Anaheim, Calif., June 2010.

Hadi Parandeh-Afshar and Paolo Ienne. Highly versatile DSP blocks for improved FPGA arithmetic performance. In Proceedings of the 18th IEEE Symposium on Field-Programmable Custom Computing Machines, pages 229-36, Napa Valley, Calif., April 2010.

Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, and Paolo Ienne. Improving FPGA Performance for Carry-Save Arithmetic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(4):578-90, April 2010.

Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, and Paolo Ienne. A flexible DSP block to enhance FPGA arithmetic performance. In Proceedings of the IEEE International Conference on Field Programmable Technology, Sydney, December 2009.

Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne. An FPGA logic cell and carry chain configurable as a 6:2 or 7:2 compressor. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2(3):19:1-19:42, September 2009.

Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne. Exploiting fast carry-chains of FPGAs for designing compressor trees. In Proceedings of the 19th International Conference on Field-Programmable Logic and Applications, pages 242-49, Prague, August 2009. Best Paper Award.

Alessandro Cevrero, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, and Paolo Ienne. Using 3D integration technology to realize multi-context FPGAs. In Proceedings of the 19th International Conference on Field-Programmable Logic and Applications, pages 507-10, Prague, August 2009.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Chrysostomos Nicopoulos, Seyed Hosein Attarzadeh Niaki, Frank K. Gurkaynak, Yusuf Leblebici, and Paolo Ienne. Field programmable compressor trees: Acceleration of multi-input addition on FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2(2):13:1-13:36, June 2009.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, and Paolo Ienne. 3D configuration caching for 2D FPGAs. In Proceedings of the 17th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, page 286, Monterey, Calif., February 2009.

Seyed Hosein Attarzadeh Niaki, Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Yusuf Leblebici, Chrysostomos Nicopoulos, and Paolo Ienne. Design space exploration for field programmable counter arrays. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Atlanta, Ga., October 2008.

Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne. Improving synthesis of compressor trees on FPGAs via integer linear programming. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Munich, March 2008.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gurkaynak, Yusuf Leblebici, and Paolo Ienne. Architectural improvements for field programmable counter arrays: Enabling efficient synthesis of fast compressor trees on FPGAs. In Proceedings of the 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2008.

Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne. A novel FPGA logic block for improved arithmetic performance. In Proceedings of the 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2008.

Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne. Efficient synthesis of compressor trees on FPGAs. In Proceedings of the Asia and South Pacific Design Automation Conference, Seoul, Korea, January 2008.

Philip Brisk, Ajay K. Verma, Hadi Parandeh-Afshar, and Paolo Ienne. Enhancing FPGA performance for arithmetic circuits. In Proceedings of the 44th Design Automation Conference, San Diego, Calif., June 2007

Miljan Vuletić, Christopher Claus, Paolo Ienne, and Walter Stechele. Multithreaded virtual-memory enabled reconfigurable hardware accelerators. In Proceedings of the IEEE International Conference on Field Programmable Technology, Bangkok, December 2006.

Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Virtual memory window for application-specific reconfigurable coprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(8):910-15, August 2006.

Christophe Dubach, Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, pages 243-48, Jersey City, N.J., September 2005.

Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Seamless hardware-software integration in reconfigurable computing systems. IEEE Design and Test of Computers, 22(2):102-13, March-April 2005.

Marc Epalza, Paolo Ienne, and Daniel Mlynek. Adding limited reconfigurability to superscalar processors. In Proceedings of the 13th International Conference on Parallel Architecture and Compilation Techniques, Antibes Juan-les-Pins, France, September 2004.

Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Programming transparency and portable hardware interfacing: Towards general-purpose reconfigurable computing. In Proceedings of the 15th International Conference on Application-specific Systems, Architectures and Processors, Galveston, Tex., September 2004.

Marc Epalza, Paolo Ienne, and Daniel Mlynek. Dynamic reallocation of functional units in superscalar processors. In Proceedings of the 9th Asia-Pacific Computer Systems Architecture Conference, Beijing, September 2004.

Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Dynamic prefetching in the virtual memory window of portable reconfigurable coprocessors. In Proceedings of the 14th International Conference on Field-Programmable Logic and Applications, Antwerp, Belgium, August 2004.

Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Virtual memory window for application-specific reconfigurable coprocessors. In Proceedings of the 41st Design Automation Conference, San Diego, Calif., June 2004.

Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Virtual memory window for a portable reconfigurable cryptography coprocessor. In Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, Calif., April 2004.

Miljan Vuletić, Ludovic Righetti, Laura Pozzi, and Paolo Ienne. Operating system support for interface virtualisation of reconfigurable coprocessors. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Paris, February 2004.

Miljan Vuletić, Ludovic Righetti, Laura Pozzi, and Paolo Ienne. Operating system support for interface virtualisation of reconfigurable coprocessors. In Proceedings of the 2nd Workshop on Application Specific Processors, San Diego, Calif., December 2003.

Computer Arithmetic and Logic Synthesis

Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, and Paolo Ienne. Progressive generation of canonical irredundant sums of products using a SAT solver. In Rolf Drechsler and André Reis, editors, Advanced Logic Synthesis, chapter 8, pages 169-88. Springer, 2017.

Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert Brayton, and Paolo Ienne. Fast generation of lexicographic satisfiable assignments: Enabling canonicity in SAT-based applications. In Proceedings of the International Conference on Computer Aided Design, pages 1–8, Austin, Tex., November 2016.

Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, and Alan Mishchenko. Fast hierarchical NPN classification. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications, pages 1–4, Lausanne, Switzerland, August 2016.

Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, and Giovanni De Micheli. Heuristic NPN classification for large functions using AIGs and LEXSAT. In Proceedings of the International Conference on Theory and Applications of Satisfiability Testing, volume 9710 of Lecture Notes in Computer Science, pages 212–27, Bordeaux, July 2016. Springer. Best Paper Award Nominee.

Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert Brayton, and Paolo Ienne. Fast generation of lexicographic satisfiable assignments: Enabling canonicity in SAT-based applications. In Proceedings of the 25th International Workshop on Logic and Synthesis, Austin, Tex., June 2016. Best Student Paper Award Nominee.

Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, and Paolo Ienne. Progressive generation of canonical sums of products using a SAT solver. In Proceedings of the 25th International Workshop on Logic and Synthesis, Austin, Tex., June 2016.

Andrew Becker, Djordje Maksimović, David Novo, Muhsen Owaida, Andreas Veneris, Barbara Jobstmann, and Paolo Ienne. FudgeFactor: Syntax-guided synthesis for accurate RTL error localization and correction. In Proceedings of the 11th Haifa Verification Conference, pages 259-275, Haifa, Israel, November 2015.

Luca Amarù, Ana Petkovska, Pierre-Emmanuel Gaillardon, David Novo Bruna, Paolo Ienne, and Giovanni De Micheli. Majority-Inverter Graph for FPGA synthesis. In Proceedings of the 19th Workshop on Synthesis and System Integration of Mixed Information Technologies, pages 165-70, Jiaosi, Taiwan, March 2015.

Ana Petkovska, David Novo, Alan Mishchenko, and Paolo Ienne. Constrained interpolation for guided logic synthesis. In Proceedings of the International Conference on Computer Aided Design, San Jose, Calif., November 2014. Best Paper Award Nominee.

Ana Petkovska, David Novo, Alan Mishchenko, and Paolo Ienne. Constrained interpolation for guided logic synthesis. In Proceedings of the 23rd International Workshop on Logic and Synthesis, San Francisco, Calif., May 2014.

Andrew Becker, David Novo, and Paolo Ienne. SKETCHILOG: Sketching combinational circuits. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 152:1–152:4, Dresden, March 2014.

Andrew Becker, David Novo, and Paolo Ienne. Automated circuit elaboration from incomplete architectural descriptions. In Proceedings of the 47th Annual Asilomar Conference on Signals, Systems, and Computers, pages 391-95, Pacific Grove, Calif., November 2013.

Elisardo Antelo, David Hough, and Paolo Ienne. Guest editors’ introduction: Special section on computer
arithmetic
. IEEE Transactions on Computers, C-61(8):1057–58, August 2012.

Ana Petkovska, David Novo, Ajay K. Verma, Alan Mishchenko, and Paolo Ienne. Enhancing iterative layering with SAT solvers. In Proceedings of the 22nd International Workshop on Logic and Synthesis, Austin, Tx., June 2013.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. Iterative Layering: Optimizing arithmetic circuits by structuring the information flow. In Proceedings of the International Conference on Computer Aided Design, San Jose, Calif., November 2009.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. A decomposition algorithm to structure arithmetic circuits. In Proceedings of the 18th International Workshop on Logic and Synthesis, Berkeley, Calif., June 2009.

Ajay K. Verma, Yi Zhu, Philip Brisk, Chung-Kuan Cheng, and Paolo Ienne. Arithmetic optimization for custom instruction set synthesis. In Proceedings of the 7th IEEE Symposium on Application Specific Processors, pages 54-57, San Francisco, Calif., July 2009.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. Challenges in automatic optimization of arithmetic circuits. In Proceedings of the 19th IEEE Symposium on Computer Arithmetic, Portland, Oreg., June 2009.

Arun Paidimarri, Alessandro Cevrero, Philip Brisk, and Paolo Ienne. FPGA implementation of a single-precision Floating-point multiply-accumulator with single-cycle accumulation. In Proceedings of the 17th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, Calif., April 2009.

Amit Verma, Ajay K. Verma, Philip Brisk, and Paolo Ienne. Hybrid LZA: A near optimal implementation of the leading zero anticipator. In Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, Japan, January 2009.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-27(10):1761–74, October 2008.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. XP2: A new compact representation for manipulating arithmetic circuits. In Proceedings of the 17th International Workshop on Logic and Synthesis, Lake Tahoe, Calif., June 2008.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. Variable latency speculative addition: A new paradigm for arithmetic circuit design. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Munich, March 2008.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. Progressive decomposition: A heuristic to structure arithmetic circuits. In Proceedings of the 44th Design Automation Conference, San Diego, Calif., June 2007. Best Paper Award Nominee.

Ajay K. Verma and Paolo Ienne. Automatic synthesis of compressor trees: Reevaluating large counters. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Nice, France, April 2007.

Ajay K. Verma and Paolo Ienne. Improving XOR-dominated arithmetic circuits by exploiting dependencies between operands. In Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, Japan, January 2007. Best Paper Award Nominee.

Ajay K. Verma and Paolo Ienne. Towards the automatic exploration of arithmetic circuit architectures. In Proceedings of the 43rd Design Automation Conference, San Francisco, Calif., July 2006.

Ajay K. Verma and Paolo Ienne. Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. In Proceedings of the International Conference on Computer Aided Design, San Jose, Calif., November 2004.

Paolo Ienne and Ajay K. Verma. Automatic Arithmetic Transformations to Maximise the Use of Compressor Trees. In Proceedings of the IEEE International Workshop on Electronic Design, Test and Applications, Perth, Australia, January 2004.

Computer Architecture and High-Level Synthesis

João Vieira, Paolo Ienne, Nuno Roma, Gabriel Falcão, and Pedro Tomás. Exploiting compute caches for memory bound vector operations. In Proceedings of the International Symposium on Computer Architecture and High Performance Computing, Lyon, September 2018.

Andrea Guerrieri. Designing an RFNoC block implementing a SISO processor using High-Level Synthesis. In Proceedings of the 7th GNU Radio Conference, San Diego, Calif., September 2017.

João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, and Vitor Silva. Design space exploration of LDPC decoders using high-level synthesis. IEEE Access, 5:14600-14615, July 2017.

Zidong Du, Shaoli Liu, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Qi Guo, Xiaobing Feng, Yunji Chen, and Olivier Temam. An accelerator for high efficient vision processing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-36(2):227–40, February 2017.

Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, and Olivier Temam. ShiDianNao: Shifting vision processing closer to the sensor. In Proceedings of the 42th Annual International Symposium on Computer Architecture, pages 92-104, Portland, Oreg., June 2015.

Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, and Chengyong Wu. Retraining-based timing error mitigation for hardware neural networks. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 595-96, Grenoble, France, March 2015.

Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, and Paolo Ienne. Virtual Ways: Low-cost coherence for instruction set extensions with architecturally visible storage. ACM Transactions on Architecture and Code Optimization (TACO), 11(2):15:1–15:26, June 2014.

Theo Kluter, Philip Brisk, Edoardo Charbon, and Paolo Ienne. Way stealing: A unified data cache and architecturally visible storage for instruction set extensions. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VLSI-22(1):62–75, January 2014.

Nithin George, David Novo, Tiark Rompf, Martin Odersky, and Paolo Ienne. Making domain-specific hardware synthesis tools cost-efficient. In Proceedings of the 2013 International Conference on Field Programmable Technology, pages 120–7, Kyoto, December 2013.

Gabriel Falcao, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, and Paolo Ienne. Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case. In Proceedings of the 20th IEEE Symposium on Field-Programmable Custom Computing Machines, pages 224-31, Toronto, April 2012.

Philip Brisk, Ajay K. Verma, and Paolo Ienne. An optimal linear-time algorithm for interprocedural register allocation in high level synthesis using SSA form. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-29(7):1096-1109, July 2010.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. Fast, nearly-optimal ISE identification with I/O serialisation through maximal clique enumeration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-29(3):341-54, March 2010.

Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, and Paolo Ienne. Virtual Ways: Efficient coherence for architecturally visible storage in automatic instruction set extensions. In Xavier Martorell, Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, and Paolo Faraboschi, editors, High Performance Embedded Architectures and Compilers, volume 5952 of Lecture Notes in Computer Science, pages 126-40. Springer, Heidelberg, Germany, 2010. Best Paper Award Nominee.

Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, and Kolin Paul. A high-level synthesis flow for custom instruction set extensions for application-specific processors. In Proceedings of the Asia and South Pacific Design Automation Conference, Taipei, Taiwan, January 2010.

Panagiotis Athanasopoulos, Philip Brisk, and Paolo Ienne. Memory organization and data layout for instruction set extensions with architecturally visible storage. In Proceedings of the International Conference on Computer Aided Design, San Jose, Calif., November 2009.

Philip Brisk, Ajay K. Verma, and Paolo Ienne. Optimistic chordal coloring: A coalescing heuristic for SSA form programs. Design Automation for Embedded Systems, 13(1-2):115-37, June 2009.

Jani Boutellier, Alessandro Cevrero, Philip Brisk, and Paolo Ienne. Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. In Proceedings of the IEEE Symposium on Signal Processing Systems, pages 115-20, Tampere, Finland, October 2009.

Theo Kluter, Philip Brisk, Edoardo Charbon, and Paolo Ienne. Way stealing: Cache-assisted automatic instruction set extensions. In Proceedings of the 46th Design Automation Conference, pages 31-36, San Francisco, Calif., July 2009.

Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel Topham, and Paolo Ienne. Introducing control-flow inclusion to support pipelining in custom instruction set extensions. In Proceedings of the 7th IEEE Symposium on Application Specific Processors, pages 114-21, San Francisco, Calif., July 2009.

Philip Brisk and Paolo Ienne. On the complexity of the port assignment problem for binary commutative operators in high-level synthesis. In Proceedings of the International Symposium on VLSI Design, Automation and Test, Hsinchu, Taiwan, April 2009.

Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne. Scalable and low cost design approach for variable block size motion estimation (VBSME). In Proceedings of the International Symposium on VLSI Design, Automation and Test, Hsinchu, Taiwan, April 2009.

Theo Kluter, Philip Brisk, Edoardo Charbon, and Paolo Ienne. MPSoC design using application-specific architecturally visible communication. In Proceedings of the 4th International Conference on High Performance and Embedded Architectures and Compilers, Paphos, Cyprus, January 2009.

Theo Kluter, Philip Brisk, Paolo Ienne, and Edoardo Charbon. Speculative DMA for architecturally visible storage in instruction set extensions. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Atlanta, Ga., October 2008.

Philip Brisk, Ajay K. Verma, and Paolo Ienne. Optimistic chordal coloring: A coalescing heuristic for SSA form programs. Design Automation for Embedded Systems, November 2008.

Paolo Ienne and Peter Petrov. Guest editorial special section on application specific processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VLSI-16(10):1257–58, October 2008.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. Fast, quasi-optimal, and pipelined instruction-set extensions. In Proceedings of the Asia and South Pacific Design Automation Conference, Seoul, Korea, January 2008.

Philip Brisk, Ajay K. Verma, and Paolo Ienne. Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. In Proceedings of the International Conference on Computer Aided Design, San Jose, Calif., November 2007.

Ajay K. Verma, Philip Brisk, and Paolo Ienne. Rethinking custom ISE identification: A new processor agnostic method. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pages 125-34, Salzburg, September 2007. Best Paper Award.

Philip Brisk, Ajay K. Verma, and Paolo Ienne. An optimistic and conservative register assignment heuristic for chordal graphs. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pages 209-17, Salzburg, September 2007.

Philip Brisk, Ajay K. Verma, and Paolo Ienne. Optimal polynomial-time interprocedural register allocation for high-level synthesis using the SSA form. In Proceedings of the 16th International Workshop on Logic and Synthesis, San Diego, Calif., May 2007.

Partha Biswas, Nikil Dutt, Laura Pozzi, and Paolo Ienne. Introduction of architecturally visible storage in instruction set extensions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-26(3), March 2007.

Jason Brown and Marc Epalza. Automatically Identifying and Creating Accelerators Directly from C Code. Xcell Journal, (58):58-60, Third Quarter 2006.

Paolo Ienne and Rainer Leupers, editors. Customizable Embedded Processors. Systems on Silicon Series. Morgan Kaufmann, San Mateo, Calif., 2006.

Paolo Ienne and Rainer Leupers. From prêt-à-porter to tailor-made. In Paolo Ienne and Rainer Leupers, editors, Customizable Embedded Processors, Systems on Silicon Series, chapter 1. Morgan Kaufmann, San Mateo, Calif., 2006.

Laura Pozzi and Paolo Ienne. Automatic instruction-set extension. In Paolo Ienne and Rainer Leupers, editors, Customizable Embedded Processors, Systems on Silicon Series, chapter 7. Morgan Kaufmann, San Mateo, Calif., 2006.

Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, and Paolo Ienne. ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(7):754-62, July 2006.

Laura Pozzi, Kubilay Atasu, and Paolo Ienne. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(7):1209-29, July 2006.

Partha Biswas, Nikil Dutt, Paolo Ienne, and Laura Pozzi. Automatic identification of application-specific functional units with architecturally visible storage. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 212-17, Munich, March 2006. Best Paper Award Nominee.

Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Paolo Ienne, and Laura Pozzi. Performance and energy benefits of instruction set extensions in an FPGA soft core. In Proceedings of the 19th International Conference on VLSI Design, pages 651-56, Hyderabad, India, January 2006. Best Paper Award Nominee.

Laura Pozzi and Paolo Ienne. Exploiting pipelining to relax register-file port constraints of instruction-set extensions. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pages 2-10, San Francisco, Calif., September 2005.

Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, and Paolo Ienne. ISEGEN: generation of high-quality instruction set extensions by iterative improvement. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Munich, March 2005.

Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, and Paolo Ienne. Fast automated generation of high-quality instruction set extensions for processor customization. In Proceedings of the 3rd Workshop on Application Specific Processors, Stockholm, September 2004.

Diviya Jain, Anshul Kumar, Laura Pozzi, and Paolo Ienne. Automatically customising VLIW architectures with coarse grained application-specific functional units. In Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems, Amsterdam, September 2004.

Partha Biswas, Kubilay Atasu, Vinay Choudhary, Laura Pozzi, Nikil Dutt, and Paolo Ienne. Introduction of local memory elements in instruction set extensions. In Proceedings of the 41st Design Automation Conference, San Diego, Calif., June 2004.

Kubilay Atasu, Laura Pozzi, and Paolo Ienne. Automatic application-specific instruction-set extensions under microarchitectural constraints. International Journal of Parallel Programming, 31(6), December 2003.

Armita Peymandoust, Laura Pozzi, Paolo Ienne, and Giovanni De Micheli. Automatic Instruction-Set Extension and Utilization for Embedded Processors. In Proceedings of the 14th International Conference on Application-specific Systems, Architectures and Processors, The Hague, The Netherlands, June 2003.

Kubilay Atasu, Laura Pozzi, and Paolo Ienne. Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints. In Proceedings of the 40th Design Automation Conference, Anaheim, Calif., June 2003. Best Paper Award (Embedded-Systems).

Ajay Kumar Verma, Kubilay Atasu, Miljan Vuletić, Laura Pozzi, and Paolo Ienne. Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints. In Proceedings of the 1st Workshop on Application Specific Processors, Istanbul, November 2002.

Bhuvan Middha, Varun Raj, Anup Gangwar, Anshul Kumar, M. Balakrishnan, and Paolo Ienne. A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units. In Proceedings of the 15th International Symposium on System Synthesis, Kyoto, October 2002.

Laura Pozzi, Miljan Vuletić, and Paolo Ienne. Automatic topology-based identification of instruction-set extensions for embedded processors. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, page 1138, Paris, March 2002.

Paolo Ienne, Laura Pozzi, and Miljan Vuletić. On the limits of processor specialisation by mapping dataflow sections on ad-hoc functional units. Technical Report 01/376, Swiss Federal Institute of Technology Lausanne (EPFL), Computer Science Department (DI), Lausanne, December 2001.

Laura Pozzi, Miljan Vuletić, and Paolo Ienne. Automatic topology-based identification of instruction-set extensions for embedded processors. Technical Report 01/377, Swiss Federal Institute of Technology Lausanne (EPFL), Computer Science Department (DI), Lausanne, December 2001.

Cryptographic Engineering and Security

Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, and Paolo Ienne. Arbitrary precision and complexity tradeoffs for gate-level information flow tracking. In Proceedings of the 54th Design Automation Conference, pages 5:1–5:6, Austin, Tex., June 2017.

Wei Hu, Andrew Becker, Armita Ardeshiri, Yu Tai, Paolo Ienne, Dejun Mu, and Ryan Kastner. Imprecise security: Quality and complexity tradeoffs for hardware information flow tracking. In Proceedings of the International Conference on Computer Aided Design, pages 1–8, Austin, Tex., November 2016.

Francesco Regazzoni and Paolo Ienne. Instruction set extensions for secure applications. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 1529–34, Dresden, March 2016.

Ali Galip Bayrak, Francesco Regazzoni, David Novo Bruna, Philip Brisk, François-Xavier Standaert, and Paolo Ienne. Automatic application of power analysis countermeasures. IEEE Transactions on Computers, C-64(2):329-41, February 2015.

Ali Galip Bayrak, Francesco Regazzoni, David Novo Bruna, and Paolo Ienne. Sleuth: Automated verification of software power analysis countermeasures. In Cryptographic Hardware and Embedded Systems (CHES 2013), Lecture Notes in Computer Science. Springer, pages 293-310, Heidelberg, Germany, September 2013.

Ali Galip Bayrak, Nikola Velickovic, David Novo Bruna, Francesco Regazzoni, Philip Brisk, and Paolo Ienne. An EDA-friendly protection scheme against side-channel attacks. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 410-15, Grenoble, France, March 2013.

Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, and Wayne Burleson. An architecture-independent instruction shuffler to protect against side-channel attacks. ACM Transactions on Architecture and Code Optimization (TACO), 8(4):20:1-20:19, January 2012.

Francesco Regazzoni, Luca Breveglieri, Israel Koren, and Paolo Ienne. Interaction between fault attack countermeasures and the resistance against power analysis attacks. In Marc Joye and Michael Tunstall, editors, Fault Analysis in Cryptography, chapter 18. Springer, 2011.

Alessandro Cevrero, Francesco Regazzoni, Michael Schwander, Stéphane Badel, Paolo Ienne, and Yusuf Leblebici. Power-gated MOS current mode logic (PG-MCML): A power aware DPA-resistant standard cell library. In Proceedings of the 48th Design Automation Conference, pages 1014-19, San Diego, Calif., June 2011.

Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, and Paolo Ienne. A first step towards automatic application of power analysis countermeasures. In Proceedings of the 48th Design Automation Conference, San Diego, Calif., June 2011.

Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stephane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, and Paolo Ienne. A design flow and evaluation framework for DPA-resistant instruction set extensions. In Christophe Clavier and Kris Gaj, editors, Cryptographic Hardware and Embedded Systems (CHES 2009), volume 5747 of Lecture Notes in Computer Science, pages 205-19. Springer, Heidelberg, Germany, September 2009.

Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank Gurkaynak, Marco Macchetti, Zeynep Toprak, Laura Pozzi, Christof Paar, Yusuf Leblebici, and Paolo Ienne. Evaluating resistance of MCML technology to power analysis attacks using a simulation-based methodology. In Marina L. Gavrilova, Chih Jeng Kenneth Tan, and Edward D. Moreno, editors, Transactions on Computational Science IV, volume 5430 of Lecture Notes in Computer Science, pages 230-43. Springer, Heidelberg, 2009.

Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren, and Christof Paar. Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices? In Proceedings of the 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 202-10, Cambridge, Mass., October 2008.

Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, and Christof Paar. Power attacks resistance of cryptographic S-boxes with added error detection procedures. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 508-16, Rome, September 2007.

Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, and Paolo Ienne. Simulation-based methodology for evaluating DPA-resistance of cryptographic functional units with application to CMOS and MCML technologies. In Proceedings of the 7th International Symposium on Systems, Architectures, Modeling and Simulation, pages 209-14, Samos, Greece, July 2007.

Johann Großschädl, Stefan Tillich, Paolo Ienne, Laura Pozzi, and Ajay K. Verma. Combining algorithm exploration with instruction set design: A study in elliptic curve cryptography. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 218-23, Munich, March 2006.

Johann Großschädl, Stefan Tillich, Paolo Ienne, Laura Pozzi, and Ajay K. Verma. When instruction set extensions change algorithm design: A study in elliptic curve cryptography. In Proceedings of the 4th Workshop on Application Specific Processors, pages 2-9, Jersey City, N.J., September 2005.

Zeynep Toprak, Yusuf Leblebici, Ajay K. Verma, Paolo Ienne, and Christof Paar. Design of low-power DPA-resistant cryptographic functional units for pervasive computing. In Proceedings of the CRyptographic Advances in Secure Hardware Workshop, Leuven, Belgium, September 2005.

Non-Volatile Memory and Emerging Technologies

Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, and Hossein Asadi. Designing low power and durable digital blocks using shadow nano-electromechanical relays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VLSI-24(12), December 2016.

Hossein Asadi, Paolo Ienne, and Hamid Sarbazi-Azad. Introduction: Special section on architecture of future many core systems. Microprocessors and Microsystems, 46:219–20, October 2016.

Hossein Asadi, Paolo Ienne, and Hamid Sarbazi-Azad. Guest editors’ introduction: Special section on emerging memory technologies in very large scale computing and storage systems. IEEE Transactions on Computers, C-65(4):1006–9, April 2016.

Xavier Jimenez, David Novo, and Paolo Ienne. Libra: Software controlled cell bit-density to balance wear in NAND flash. ACM Transactions on Embedded Computing Systems (TECS), 14(2):28:1{28:22, March 2015.

Xavier Jimenez, David Novo, and Paolo Ienne. Wear unleveling: Improving NAND flash lifetime by balancing page endurance. In Proceedings of the 12th USENIX Conference on File and Storage Technologies, pages 47-59, Santa Clara, Calif., February 2014.

Xavier Jimenez, David Novo Bruna, and Paolo Ienne. Phoenix: Reviving MLC blocks as SLC to extend NAND flash devices lifetime. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 226-29, Grenoble, France, March 2013.

Xavier Jimenez, David Novo Bruna, and Paolo Ienne. Software controlled cell bit-density to improve NAND flash lifetime. In Proceedings of the 49th Design Automation Conference, pages 229-34, San Francisco, Calif., June 2012.

Robust Design

Maurizio Skerlj and Paolo Ienne. Error Protected Data Bus Inversion using Standard DRAM Components. In Proceedings of the 9th International Symposium on Quality Electronic Design, San Jose, Calif., March 2008.

Frédéric Worm, Patrick Thiran, and Paolo Ienne. Optimizing checking-logic for reliability-agnostic control of self-calibrating designs. In Proceedings of the 8th International Symposium on Quality Electronic Design, San Jose, Calif., March 2007.

Frédéric Worm, Patrick Thiran, and Paolo Ienne. Designing robust checkers in the presence of massive timing errors. In Proceedings of 12th IEEE International On-Line Testing Symposium, pages 281-86, Lake of Como, Italy, July 2006.

Frédéric Worm, Patrick Thiran, Giovanni De Micheli, and Paolo Ienne. Self-calibrating Networks-on-Chip. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 2361-64, Kobe, Japan, May 2005.

Dominique Tschopp, Maria Gabrani, and Paolo Ienne. Evaluating dependability options when designing future Systems-on-Chip. In Proceedings of the 10th IEEE Workshop on Dependable Parallel, Distributed and Network-Centric Systems, Denver, Colo., April 2005.

Frédéric Worm, Patrick Thiran, and Paolo Ienne. A unified coding framework for delay-insensitivity. In Proceedings of the 11th International Symposium on Asynchronous Circuits and Systems, New York, March 2005.

Frédéric Worm, Paolo Ienne, Patrick Thiran, and Giovanni De Micheli. A robust self-calibrating transmission scheme for on-chip networks. IEEE Transactions on Very Large Scale Integration (VLSI), 13(1), January 2005.

Frédéric Worm, Paolo Ienne, Patrick Thiran, and Giovanni De Micheli. On-Chip self-calibrating communication techniques robust to electrical parameter variations. IEEE Design and Test of Computers, 21(6), November-December 2004.

Frédéric Worm, Paolo Ienne, and Patrick Thiran. Soft self-synchronising codes for self-calibrating communication. In Proceedings of the International Conference on Computer Aided Design, San Jose, Calif., November 2004.

Frédéric Worm, Paolo Ienne, Patrick Thiran, and Giovanni De Micheli. An adaptive low-power transmission scheme for on-chip networks. In Proceedings of the 15th International Symposium on System Synthesis, Kyoto, October 2002

Multiprocessors, Design Methodologies, and VLSI

Paolo Ienne and Jean-Pierre-Talpin. Guest editorial: Special issue on models and methodologies for system design. ACM Transactions on Embedded Computing Systems (TECS), 15(2):29:1–29:2, May 2016.

David Novo, Nazanin Farahpour, Ubaid Ahmad, Francky Catthoor, and Paolo Ienne. Energy efficient MIMO processing: A case study of opportunistic run-time approximations. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 207:1–207:6, Dresden, March 2014.

David Novo, Irene Tzimi, Ubaid Ahmed, Paolo Ienne, and Francky Catthoor. Cracking the complexity of fixed-point refinement in complex wireless systems. In Proceedings of the IEEE Symposium on Signal Processing Systems, pages 18–23, Taipei, Taiwan, October 2013.

Lunkai Zhang, Mingzhe Zhang, Lingjun Fan, Da Wang, and Paolo Ienne. Spontaneous reload cache: Mimicking a larger cache with minimal hardware requirement. In Proceedings of the 8th IEEE International Conference on Networking, Architecture, and Storage, Xi’an, China, July 2013.

David Novo Bruna, Sara El Alaoui, and Paolo Ienne. Accuracy vs. speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pages 15-20, Grenoble, France, March 2013.

Alessandro Cevrero, Nestor Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, and George Stamoulis. Fast and accurate BER estimation methodology for I/O links based on extreme value theory. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Grenoble, France, March 2013.

Shuai Jiao, Paolo Ienne, Xiaochun Ye, Da Wang, Dongrui Fan, and Ninghui Sun. CRAW/P: A workload partition method for the efficient parallel simulation of manycores. In Proceedings of the 18th International European Conference on Parallel and Distributed Computing, pages 102-14, Rhodes Island, Greece, August 2012.

Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, and Paolo Ienne. Counting stream registers: An efficient and effective snoop filter architecture. In Proceedings of the 12th International Symposium on Systems, Architectures, Modeling and Simulation, pages 120-7, Samos, Greece, July 2012.

Alessando Cevrero, Yusuf Leblebici, Paolo Ienne, and Andreas Burg. A 5.35mm2 10GBASE-T Ethernet LDPC decoder chip in 90nm CMOS. In Proceedings of the IEEE Asian Solid-State Circuits Conference, Beijing, November 2010.

Xiaochun Ye, Dongrui Fan, Wei Lin, Nan Yuan, and Paolo Ienne. High performance comparison-based sorting algorithm on many-core GPUs. In Proceedings of the 24th IEEE International Parallel and Distributed Processing Symposium, pages 1-10, Atlanta, Ga., April 2010.

Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, and Paolo Ienne. A predictable communication
scheme for flexible embedded multiprocessors
. In Proceedings of the 14th IEEE/IFIP International
Conference on VLSI and System-on-Chip, pages 152-57, Nice, France, October 2006.

Soner Yaldiz, Alper Demir, Serdar Tasiran, Yusuf Leblebici, and Paolo Ienne. Characterizing and exploiting task-load variability and correlation for energy management in multi-core systems. In Proceedings of the 3rd IEEE Workshop on Embedded Systems for Real Time Multimedia, pages 129-40, Jersey City, N.J., September 2005.

Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, and Paolo Ienne. Quantitative modelling and comparison of communication schemes to guarantee Quality-of-Service in Networks-on-Chip. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 1782-85, Kobe, Japan, May 2005.

Derin Harmanci, Nuria Pazos, Paolo Ienne, and Yusuf Leblebici. Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. In Proceedings of the International Symposium on System-on-Chip, pages 37-40, Tampere, Finland, November 2004.

Nuria Pazos, Alexander Maxiaguine, Paolo Ienne, and Yusuf Leblebici. Parallel modelling paradigm in multimedia applications: Mapping and scheduling onto a multi-processor system-on-chip platform. In Proceedings of the International Global Signal Processing Conference, Santa Clara, Calif., September 2004.

Miscellanea

Claudio Favi, Xavier Jimenez René Beuchat, and Paolo Ienne. From gates to multi-processors: Learning systems hands-on with FPGA4U in a computer science programme. In Proceedings of the Workshop on Embedded Systems Education, Grenoble, France, October 2009.

Marc A. Viredaz and Paolo Ienne. MANTRA I: A systolic array for neural computation. In David Zhang and Sankar K. Pal, editors, Neural Networks and Systolic Array Design, Machine Perception and Artificial Intelligence. World Scientific, Singapore, 2002.